The present invention relates generally to signal generators, and, more particularly, to a signal generator utilizing a frequency locked-loop having very fast frequency switching times to provide an output signal which switches from frequency to frequency in a selectable sequence.
Signal generators utilizing phase-locked-loop apparatus to provide an output signal having a precise, stable frequency are well known in the art. Such a phase-locked-loop (PLL) includes a tunable oscillator, typically a voltage controlled oscillator (VCO) whose output is locked to a known reference signal by means of a phase comparator. The phase comparator generates an output voltage or current that is proportional to the phase difference between the two signals. The phase comparator output is fed back to the input of the VCO to tune the VCO to the desired frequency. This forces the VCO output signal to have the same frequency as the reference signal. By interposing a divide-by-N block in the circuit comparator, the reference frequency may instead be compared with the VCO output frequency divided by N; the VCO output will then be locked to N times the reference frequency. Another technique, called fractional-N, makes it possible to generate frequencies that are any rational multiple of the reference frequency. Such a technique is disclosed in U.S. Pat. No. 3,928,813 issued to Charles A. Kingsford-Smith on Dec. 23, 1975 entitle "Device for Synthesizing Frequencies Which are Rational Multiples of a Fundamental Frequency" .
In some applications, it is often desired to generate an output signal whose frequency shifts or hops from one frequency value to another frequency value at selected intervals of time. In such applications, it is desireable for the apparatus to stabilize at the new frequency in as short a time as possible; i.e., a low settling time. U.S. Pat. No. 4,568,888 entitled "PLL Fast Frequency Synthesizer With Memories for Coarse Tuning and Loop Gain Correction" issued to Robert K. Kimura on Feb. 4, 1986 discloses a signal synthesizer employing a phase-locked loop that provides an output signal whose frequency may be selectively changed from one value to another having a reduced settling time and a substantially uniform loop gain over its entire frequency range. To achieve a low settling time at each new frequency, the frequency synthesizer includes coarse tuning means for immediately applying to the VCO a signal level having a selected value that coarsely adjusts the VCO to the new desired frequency. This coarse tuning means, includes memory means for storing information indicating the nominal signal value required by the VCO to produce each frequency in the predetermined frequency range. The coarse tuning information may be adjusted to reflect any changes in the VCO's gain frequency constant over time and temperature.